Manufacturing of an integrated circuit (IC) has been largely driven by the need to increase the density of the integrated circuit formed in a semiconductor device. This is typically accomplished by implementing more aggressive design rules to allow larger density of IC device to be formed. Nonetheless, the increased density of the IC devices has also increased the complexity of processing semiconductor devices with the decreased feature sizes.
The IC device is an integrated circuit (IC) chip, system on chip (SoC), or portion thereof, that includes various passive and active microelectronic components, such as metal-oxide-semiconductor field effect transistors (MOSFETs). Being basic logic building blocks in the formation of the IC, semiconductor manufactures utilize a wide variety of techniques to improve the performance of the MOSFETs. The performance of MOSFETs may be increased by enhancing the carrier mobility of silicon, so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A way of enhancing carrier mobility is the introduction of strained structures in source/drain recess cavities of the MOSFET, which includes a p-type metal-oxide-semiconductor (PMOS) and an n-type metal-oxide-semiconductor (NMOS), utilizing selectively grown silicon germanium (SiGe). However, there are challenges to implement such features in MOSFET. As the gate length decrease, the problems become obvious. For example, the effect of ion implantation depth and doped profile in the source/drain regions to the threshold voltage become significant.